In a number of electronic systems, the memory devices are used to store recovery data necessary for restoring a working environment in case the power supply goes down.
For example, when the power supply is cut off abruptly in a computer (due to an interruption of the electric power or any mistake of the user), recovery data have to be stored in the memory devices just before the power down, so that when the power supply is applied again to the computer, the working environment related to the former state preceding the power down is restored using the recovery data. Such operation is also called a “hibernation operation”.
Typically, non-volatile memory devices (such as conventional flash or EEPROM memories) are employed for storing the recovery data during the hibernation operation. The data are safely saved by programming the non-volatile memory devices, and the programmed data are preserved even when the memory device power supply is off.
Unfortunately, the program operation of flash or EEPROM memories may require a significantly long time, so that these memories may be unsuitable for applications where the hibernation operation has to be performed in a very short time (ranging for example from 50 μs to 500 μs).
In more detail, the flash memory devices are electrically-programmable, non-volatile memories, with memory cells consisting of a floating-gate MOS transistor, which stores a logic value defined by its threshold voltage (which depends on the electric charge stored on the floating gate). In particular, during the programming operation of the floating-gate MOS transistor electrons are injected, for example by means of the known Fowler-Nordheim tunneling mechanism, into the floating gate; the retention of such electrons by the floating gate guarantees the memory device non-volatility. Vice versa, during the erasing operation, the floating gate is substantially emptied of the electrons, which were injected during the programming.
In a flash memory, every single memory cell may be programmed individually, but memory cells cannot be individually erased: a large number of memory cells, forming a so-called “memory sector”, are erased at the same time.
In a flash memory device with NAND architecture, which ensures a high degree of compactness, the memory cells are grouped in strings, each one consisting of a group of memory cells that are connected in series between a drain select transistor, connected to a bit line, and a source select transistor, connected to a reference voltage distribution line distributing a reference voltage (such as a ground voltage); groups of said strings of memory cells are connected to a same bit line, and thus they are connected in parallel to each other.
Memory cells are programmed by repeatedly applying thereto programming voltage pulses.
During a reading operation, the select lines of the string including the selected memory cell to be read are brought to the supply voltage. The word line of the selected memory cell is brought to a read voltage which is intermediate between the threshold voltage range corresponding to the “1” state and the threshold voltage range corresponding to the “0” state; for example, the read voltage may be equal to the reference voltage (0V). The other word lines, to which the other memory cells of the string belong, are brought to a passing voltage Vpass having a value (for example, 4.5V) sufficiently high to ensure that the memory cells connected thereto are rendered conductive irrespective of their threshold voltage, i.e. irrespective of the fact that they are programmed or not.
Thus, by using the reference voltage as a reading voltage value, the selected memory cell of the string will be conductive if its threshold voltage is lower than the gate-source voltage applied thereto, and not conductive otherwise; this allows discriminating the data stored in the memory cells.
In order to ensure that all the other memory cells of string, other than the selected memory cell, are conductive, the passing voltage Vpass is chosen sufficiently higher than the expected maximum threshold voltage of the memory cells of the string. If even one memory cell happens to have a threshold voltage higher than the expected maximum threshold voltage, the latter may remain non-conductive when the passing voltage Vpass is applied thereto, and this causes errors of the read logic value.
Such problem may be magnified by the fact that during each reading operation, spurious hot carrier generation occurs that cause soft programming of the unselected memory cells. In such case, the threshold voltage of some memory cells may become higher that the expected maximum threshold voltage, so that even applying thereto the passing voltage Vpass those memory cells do not turn on, causing reading errors.
For limiting the occurrence of these problems, the width of the statistical distribution of the threshold voltages of the programmed cells should be tightly controlled, so that the threshold voltage varies in a quite narrow range of values (for example, 3V). In order to ensure that the width of the memory cells threshold voltages distribution remains within the desired range, several verify operations are to be performed, after each programming pulse. The need to apply several programming pulses and to perform several program verify lengthens the time required for programming the memory.